Ball grid array (BGA) semiconductor packages adopt advanced and widely employed packaging technology, which is characterized by using a plurality of array-arranged solder balls as input/output (I/O) ports of the semiconductor packages for electrically connecting chips mounted in the semiconductor packages to external devices such as printed circuit boards.
U.S. Pat. No. 5,216,278 discloses a BGA semiconductor package with a substrate as a chip carrier, which can be fabricated by the following procedural steps. As shown in FIG. 6A, the first step is to prepare a substrate 10 formed with at least a layer of metal traces (not shown), the substrate 10 having an upper surface 100 and a lower surface 101 opposed to the upper surface 100. The upper and lower surfaces 100, 101 are each formed with a plurality of copper-made conductive traces 11 thereon. A solder mask layer 12 is applied over each of the upper and lower surfaces 100, 101 for encapsulating the conductive traces 11, allowing terminals 110, 111 of the conductive traces 11 to be exposed to outside of the solder mask layers 12 The next step is to mount at least a chip 13 on the upper surface 100 of the substrate 10. Then, a plurality of bonding wires 14 are bonded to the chip 13 and to the exposed terminals 110 used as bond fingers on the upper surface 100 of the substrate 10, so as to electrically connect the chip 13 to the substrate 10 by means of the bonding wires 14; the exposed terminals 111 on the lower surface 101 of the substrate 10 are used as ball pads where solder balls (not shown) may be subsequently implanted. Thereafter, a molding process is performed to form at least an encapsulant 15 on the upper surface 100 of the substrate 10, the encapsulant 15 being adapted to hermetically encapsulate the chip 13 and the bonding wires 14.
After molding, as shown in FIG. 6B, the substrates 10 mounted with the chips 13 are vertically stacked in a back-to-back manner with the lower surfaces 101 thereof being in contact with each other, and readily subject to a post molding curing (PMC) process, wherein the stacked substrates 10 are clamped at peripheral part thereof by a clamping mechanism (not shown), which applies a pressure P to the substrates 10 for securing the substrates 10 in position without being warped during a subsequent curing process. Then, the stacked substrates 10 are placed into an oven (not shown), and undergo curing implemented at around 175° C. for around 6 hours, so as to allow a resin compound that fabricates the encapsulants 15 to form cross-link between high molecular-weight molecules thereof and thus to be cured. After completing the PMC process, the stacked substrates 10 are removed from the oven (not shown), and a thin blade or iron plate (not shown) is used to separate apart the inter-contact lower surfaces 101 of the stacked substrates 10, as shown in FIG. 6C. Finally, ball-implantation and singulation processes are carried out to form individual semiconductor packages; these processes are conventional and not to be here illustrated by drawings.
However, during the PMC process, the solder mask layers 12 on the inter-contact lower surfaces 101 of the stacked substrates 10 are pressurized and heated to be softened and adhered to each other, thereby increasing adhesion between the stacked substrates 10. As a result, during separating the stacked substrates 10, the thin blade or iron plate (not shown) may be easily introduced at inaccurate or deviated positions, for example, along a direction of an arrow S shown in FIG. 6B to cut into the solder mask layer 12 of the lower surface 101 of the upper substrate 10 (or the lower substrate 10, not indicated by an arrow in FIG. 6B); this would undesirably crack the solder mask layer 12 (as circled in FIG. 6C), and damage quality and yield of fabricated package products.